With the increasing use of large digital application specific integrated circuits (ASICs), built-in-self-test (BIST) is becoming a preferred method for meeting stringent testability, fault-detection, and fault-isolation requirements. BIST reduces external automatic test equipment complexity by moving many of the external testing functions onto the chip itself. The penalty paid for BIST is extra silicon area overhead and circuit speed degradation.
One of the more effective and efficient self-test methodologies for digital circuit designs is known as circular built-in-self-test, or CBIST. CBIST is a structural self-test technique which is based upon the use of a scan-path to apply pseudo-random pattern stimulus to the circuit-under-test and to observe and compress its response.
What is needed is an automated method for selecting and inserting testpoints into a netlist describing an electrical circuit which brings fault coverage for a CBIST self-test to a predetermined level.